1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device into which data is electrically written and from which data is electrically erased, and more particularly to a nonvolatile semiconductor memory device into which data is written by using a tunnel current and to a method of manufacturing the nonvolatile semiconductor memory device.
2. Description of the Related Art
FIG. 1 is a sectional view of a conventional non-volatile semiconductor memory. This memory has been manufactured in the following steps. First, a P-type well layer 2 is formed in the surface of an N-type silicon substrate 1. Then, an element isolating region 3 is formed in the surface of the P-type well layer 2. Thereafter, a gate insulating film 4 is formed on the P-type well layer 2. A first polysilicon layer 5a is deposited on the gate insulating film 4. Phosphorus is diffused into the polysilicon layer 5a, thereby adding phosphorus to the layer 5a. Next, an ONO film 6 is deposited on the first polysilicon layer 5a. The ONO film 6 has a three-layer structure, comprised of the lower layer made of oxide, the intermediate layer made of nitride and the upper layer made of oxide. Further, a second polysilicon layer 7a is deposited on the ONO film 6. Phosphorus is diffused into the second polysilicon layer 7a, thereby adding phosphorus to the layer 7a.
Next, the polysilicon layers 5a and 7a and the ONO film 6 are subjected to photolithography. A floating gate 5 is thereby formed on the gate insulating film 4, and an a control gate 7 is formed on the ONO film 6 and located above the floating gate 5. Thereafter, ions are implanted into the P-type well layer 2, using the control gate 7 and the element isolating region 4 as 10 masks. Two N-type diffusion layers 8, which serve as a source region and a drain region, respectively, are thereby formed in the P-type well layer 2. Then, an insulating film 9 is formed on the sides of the floating gate 5 and on the sides and upper surface of the control gate 7.
How data is written into the conventional nonvolatile semiconductor memory will be explained below.
The P-type well layer 2 and the N-type diffusion layers 8 (i.e., the source and drain regions) are connected to the ground, and a programming voltage v.sub.ppw, which is of a positive value, is applied to the control gate 7. As a result, capacitance C.sub.FC is built up in a capacitor constituted by the floating gate 5 and the control gate 7, and capacitance C.sub.FW is built up in a capacitor constituted by the floating gate 5 and the P-type well layer 2. By virtue of the capacitances C.sub.FC and C.sub.FW, the programming voltage v.sub.ppw is divided into a voltage V.sub.FC and a voltage V.sub.FW, which are represented by Equations (1) and (2) given below. The voltage V.sub.FC is applied between the floating gate 5 and the control gate 7. The voltage V.sub.FW is applied between the floating gate 5 and the P-type well layer 2. The voltage V.sub.FW is applied on the gate insulating film 4, whereby an N-type inversion layer is formed in that surface region of the P-type well layer 2 which lies below the floating gate 5. The source region and the drain region are thereby set at the same potential. Since the N-type diffusion layers 8 (i.e., the source and drain regions) are grounded, the N-type inversion layer is set at the ground potential. Hence, a positive voltage is virtually applied to the floating gate 5 provided on the insulating film 4 which in turn is provided on the N-type silicon substrate 1.
Therefore, a current having density J which is represented by Equation (3) flows to the floating gate 5. Electrons are thereby injected into the floating gate 5, and data is written into the transistor. Once the data has been written into the transistor, the threshold voltage of the transistor must remain within a prescribed allowable range. EQU VFC=CFW.v.sub.ppw /(C.sub.FC +C.sub.fW) (1) EQU VFW=CFC.v.sub.ppw /(C.sub.FC +C.sub.FW) (2) EQU J=.alpha.(v.sub.FW /T.sub.OX).sup.2. exp(-.beta..T.sub.OX /V.sub.FW)(3)
In Equation (3), T.sub.OX is the thickness of the gate insulating film 4 and .alpha. and .beta. are proportionality constants.
When the current having density J represented by Equation (3) flows to the floating gate 5, a small change in V.sub.FW /T.sub.OX causes a large change in the current density J as can be understood from Equation (3). The change of V.sub.FW /T.sub.OX, though small, results from changes in the manufacturing conditions of the conventional nonvolatile semiconductor memory. The intensity of the electric field applied on the gate insulating film 4 changes, and the density J of the current flowing to the floating gate 5 varies inevitably. The threshold voltage of the transistor changes unavoidably. The greater the number of electrons injected into the floating gate 5, the larger the change of the threshold voltage. Consequently, in the conventional memory it is difficult to hold the threshold voltage of the transistor within the prescribed allowable range.
In other words, as is evident from FIG. 2, the current I supplied to the floating gate changes greatly even if the difference between the maximum intensity 10b and minimum intensity 10a of the electric field E (=V.sub.FW /T.sub.OX) is small. Many of the transistors incorporated in the conventional memory have their threshold voltage much changed as shown in FIG. 3 after data has been written into them. For this reason, the conventional nonvolatile semiconductor memory can be manufactured but at a low yield.